Publications

2025

• Yuanlong Li, Atri Bhattacharyya, Madhur Kumar, Abhishek Bhattacharjee, Yoav Etsion, Babak Falsafi, Sanidhya Kashyap, and Mathias Payer.
  Single-Address-Space FaaS with Jord.
  In Intl. Conf. Computer Architecture (ISCA), June 2025 (to appear).

2022

• Oren Kalinsky, Aiden Hogan, Oren Mishali, Yoav Etsion, and Benny Kimelfeld.
  Exploration of Knowledge Graphs via Online Aggregation.
  In Intl. Conf. on Data Engineering (ICDE), May 2022.

2021

• Oron Port and Yoav Etsion.
  Registerless Hardware Description.
  In Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), Apr 2021.

2020

• Oren Kalinsky, Benny Kimelfeld, and Yoav Etsion.
  The TrieJax Architecture: Accelerating Graph Operations Through Relational Joins.
  In Intl. Conf. on Architectural Support for Programming Languages and Operating
  Systems (ASPLOS), Mar 2020.

2019

• Leeor Peled, Uri C. Weiser, and Yoav Etsion.
  A Neural Network Prefetcher for Arbitrary Memory Access Patterns.
  In ACM Trans. on Architecture and Code Optimizations 16(4), Oct 2019.
• Lluis Vilanova, Nadav Amit, and Yoav Etsion.
  Using SMT to Accelerate Nested Virtualization.
  In Intl. Symp. on Computer Architecture (ISCA), June 2019.
• Lluis Vilanova, Yoav Etsion, and Mark Silberstein.
  One Interface to Rule Them All: A Hardware/Software Co-Design for Disaggregated Computing.
  In 9th Workshop on Systems for Multi-core and Heterogeneous Architectures, Mar 2019.

2018

• Dani Voitsechov, Oron Port, and Yoav Etsion.
  “Inter-thread Communication in Multithreaded, Reconfigurable Coarse-grain Arrays“.
  In Intl. Symp. on Microarchitecture (MICRO-51), Oct 2018
• Oren Kalinsky, Oren Mishali, Aiden Hogan, Yoav Etsion, and Benny Kimelfeld.
  “Efficiently charting RDF“.
  In arXiv preprint arXiv:1811.10955.
• Eran Gilad, Trevor Brown, Mark Oskin, and Yoav Etsion.
  “Snapshot-based Synchronization: A Fast Replacement for Hand-over-Hand Locking“.
  In EuroPar, Aug 2018.
• Casen Hunger, Lluis Vilanova, Charalampos  Papamanthou, Yoav Etsion, and Mohit Tiwari.
  “DATS – Refactoring Access Control Out of Web Applications“.
  In Intl. Conf. on Arch. Support for Programming Languages and Operating Systems (ASPLOS), Mar 2018.
• Eran Gilad, Tehila Mayzels, Elazar Raab, Mark Oskin, and Yoav Etsion.
  “Architectural Support for Unlimited Memory Versioning and Renaming“.
  In Intl. Parallel and Distributed Processing Symp. (IPDPS), May 2018.

2017

• Eran Gilad, Tehila Mayzels, Elazar Raab, Mark Oskin, and Yoav Etsion.
  “Towards a Deterministic Fine-grained Task Ordering using Multi-Versioned Memory“.
  In Intl. Symp. on Computer Architecture and High Performance Computing (SBAC-PAD), Oct 2017.
• Oron Port and Yoav Etsion.
  “DFiant: A Dataflow Hardware Description Language“.
  In Intl. Conf. on Field-Programmable Logic and Applications (FPL), Sep 2017 (poster)
• Hanna Alam, Tianhao Zhang, Mattan Erez, and Yoav Etsion.
  “Do-It-Yourself Virtual Memory Translation“.
  In Intl. Symp. on Computer Architecture (ISCA), Jun 2017.
• Lluís Vilanova, Marc Jordà, and Nacho Navarro, Yoav Etsion, and Mateo Valero.
  “Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC“.
  In EuroSys, Apr 2017.
• Oren Kalinsky, Yoav Etsion, and Benny Kimelfeld.
  “Flexible Caching in Trie Joins“.
  In Intl. Conf. on Extending Database Technology (EDBT), Mar 2017.

2016

• Yonatan Gottesman  and Yoav Etsion.
  “NeSC: Self Virtualizing Nested Storage Controller“.
  In Intl. Symp. on Microarchitecture (MICRO-49), Oct 2016
• Oren Kalinsky, Yoav Etsion, and Benny Kimelfeld.
  “Flexible Caching in Trie Joins”.
  In CoRR abs/1602.08721, Feb 2016

2015

• Dani Voitsechov and Yoav Etsion.
  “Control Flow Coalescing on a Hybrid Dataflow/von Neumann GPGPU”.
  In Intl. Symp. on Microarchitecture (MICRO-48), Dec 2015
•  Leeor Peled, Shie Mannor, Uri Weiser and Yoav Etsion.
  “Semantic Locality and Context-based Prefetching Using Reinforcement Learning”.
  In Intl. Symp. on Computer Architecture (ISCA), Jun 2015

2014

• Adi Fuchs, Shie Mannor, Uri Weiser and Yoav Etsion.
  “Loop-Aware Memory Prefetching Using Code Block Working Sets”.
  In Intl. Symp. on Microarchitecture (MICRO-47), Dec 2014
• Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Avinoam Kolodny, Uri C. Weiser, Ravi Patel and Eby G. Friedman.
  “Memristive multistate pipeline register”.
  In Intl. Workshop on Cellular Nanoscale Networks and their Applications (CNNA), July 2014
• Dani Voitsechov and Yoav Etsion.
  “Single-Graph Multiple Flows: Energy Efficient Design Alternative for GPGPUs”.
  In Intl. Symp. on Computer Architecture (ISCA), June 2014
• Lluis Vilanova, Muli Ben-Yehuda, Nacho Navarro, Yoav Etsion and Mateo Valero.
  “CODOMs: Protecting Software with Code-centric Memory Domains”.
  In Intl. Symp. on Computer Architecture (ISCA), June 2014
• Eran Gilad, Eric W Mackay, Mark Oskin, Yoav Etsion.
  “O-structures: Semantics for Versioned Memory”.
  In ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC), June 2014
•  Fahimeh Yazdanpanaha, Carlos Alvarez-Martinez, Daniel Jimenez-Gonzalez, Yoav Etsion.
  “Hybrid Dataflow/von-Neumann Architectures”.
  In IEEE Trans. on Parallel and Distributed Systems (TPDS) 25(6), June 2014.
  The paper includes an online supplemental appendix.

2013

• Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, and Uri. C. Weiser.
  “Memristor-based Multithreading”
  In IEEE Computer Architecture Letters (CAL) (PrePrint).
• Fahimeh Yazdanpanaha, Daniel Jimenez-Gonzalez, Carlos Alvarez-Martinez, Yoav Etsion, Rosa M. Badia.
  “Analysis of the Task Superscalar Architecture Hardware Design”
  In Intl. Conf. on Computational Science (ICCS), Jun 2013.

2012

• Yoav Etsion and Dror G. Feitelson.
  “Exploiting Core Working Sets to Filter the L1 Cache with Random Sampling”
  In IEEE Transactions on Computers (TC), 61(11), pp. 1535-1550, Nov 2012.
• Nathaniel Azuelos, Eduard Ayguade, Idit Keidar, Ayal Zaks and Yoav Etsion.
  “Introducing Speculative Optimizations in Task Dataflow with Language Extensions and Runtime Support”
  In Workshop on Data-Flow Execution Models for Extreme Scale Computing (DFM), Sep 2012.
• E. Ayguadé, R. M. Badia, P. Bellens, J. Bueno-Hedo, A. Duran, Y. Etsion, M. Farreras, R. Ferrer, J.
  Labarta, V. Marjanovic, L. Martinell, X. Martorell, J. M. Pérez, J. Planas, A. Ramirez, X. Teruel, I. Tsalouchidou, M. Valero.
  “Hybrid/Heterogeneous Programming with OmpSs and its Software/Hardware Implications”
  In Programming Multi-Core and Many-Core Computing Systems (Wiley Series on Parallel and Distributed Computing), Sabri Pllana and Fatos Xhafa (Eds.), John Wiley & Sons, Inc., 2012
• Alejandro Rico, Felipe Cabarcas, Carlos Villavieja, Milan Pavlovic, Augusto Vega, Yoav Etsion, Alex Ramirez, and Mateo Valero.
  “On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels”
  In ACM Trans. on Architecture and Code Optimization (TACO), 8(4), Jan 2012.
  Selected for presentation at the HiPEAC Conf., Jan 2012.

2011

• Milan Pavlovic, Yoav Etsion, and Alex Ramirez.
  “On the Memory System Requirements of Future Scientific Applications: Four Case Studies”
  In IEEE Intl. Symp. on Workload Characterization (IISWC), Nov 2011.
• Miquel Pericàs, Xavier Martorell, and Yoav Etsion.
  “Implementation of a hierarchical N-body simulator using the Ompss programming model”
  In Workshop on Irregular Applications: Architectures and Algorithm (IAAA), Oct 2011.
• Carlos Villavieja, Vasilis Karakostas, Lluis Vilanova, Yoav Etsion, Alex Ramirez, Avi Mendelson, Nacho Navarro, Adrian Cristal, Osman Unsal.
  “DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory”
  In Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), Oct 2011.
• Carlos Villavieja, Yoav Etsion, Alex Ramirez, and Nacho Navarro.
  “FELI: HW/SW support for On-Chip Distributed Shared Memory in Multicores”
  In Euro-Par, Aug 2011.
• Alejandro Rico, Alex Duran, Felipe Cabarcas, Alex Ramirez, Yoav Etsion, and Mateo Valero.
  “Trace-driven Simulation of Multithreaded Applications”
  In Intl. Symp. Performance Analysis of Systems and Software (ISPASS), Apr 2011.

2010

• Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramirez, Rosa M. Badia, Eduard Ayguade, Jesus Labarta, and Mateo Valero.
  “Task Superscalar: An Out-of-Order Task Pipeline”.
  In IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43), Dec 2010.
• Felipe Cabarcas, Alejandro Rico, Yoav Etsion, and Alex Ramirez.
  “Interleaving Granularity on High Bandwidth Memory Architecture for CMPs”.
  In Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Jul 2010.
• Yoav Etsion, Alex Ramirez, Rosa M. Badia, Eduard Ayguade, Jesus Labarta, and Mateo Valero.
  “Task Superscalar: Using Processors as Functional Units”.
  In USENIX Workshop on Hot Topics In Parallelism (HotPar), Jun 2010.
• Milan Pavlovic, Yoav Etsion, and Alex Ramirez.
  “Can Manycores Support the Memory Requirements of Scientific Applications?”.
  In Workshop on Applications for Multi and Many Core Processors (A4MMC), Jun 2010.
  Awarded Best Paper
• Tal Ben-Nun, Yoav Etsion, and Dror G. Feitelson.
  “Design and Implementation of a Generic Resource Sharing Virtual Time Dispatcher”.
  In SYSTOR, May 2010.

2009

• Yoav Etsion, Alex Ramirez, Rosa M. Badia, and Jesus Labarta.
  “Cores as Functional Units: A Task-Based, Out-of-Order, Dataflow Pipeline” (extended abstract).
  In Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), Jul 2009.
• Yoav Etsion, Tal Ben-Nun, and Dror G. Feitelson.
  “A Global Scheduling Framework for Virtualization Environments.”
  In Workshop on System Management Techniques, Processes and Services (SMTPS), May 2009.
  Awarded Best Student Paper

2008

• Yoav Etsion.
  The Skewed Distribution of Working Sets: Leveraging Randomness for Cache Design .
  PhD Dissertation. Sep 2009.
• Yoav Etsion and Dror G. Feitelson.
  Core Working Sets: Concept, Identification, and Use .
  Technical Report 2008-64, School of Computer Science and Engineering, The Hebrew University of Jerusalem, Jul. 2008.
• Tal Ben-Nun, Yoav Etsion and Dror G. Feitelson.
  The Klogger Networking Schema .
  Technical Report 2008-1, School of Computer Science and Engineering, The Hebrew University of Jerusalem, Jan. 2008.

2007

• Yoav Etsion and Dror G. Feitelson.
  “L1 Cache Filtering Through Random Selection of Memory References” .
  In Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), pp. 235-244, Sep 2007.
• Dan Tsafrir, Yoav Etsion, and Dror G. Feitelson.
  “Secretly monopolizing the CPU without superuser privileges” .
  In 16th USENIX Security Symposium, Aug 2007.
• Dror G. Feitelson, Tokunbo O. S. Adeshiyan, Daniel Balasubramanian, Yoav Etsion, Gabor Madl, Esteban P. Osses, Sameer Singh, Karlkim Suwanmongkol, Charlie Xie, and Stephen R. Schach.
  “Fine-Grain Analysis of Common Coupling and its Application to a Linux Case Study.”
  In Journal of Systems and Software (JSS), 80(8), pp. 1239-1255, Aug 2007.
• Dan Tsafrir, Yoav Etsion, and Dror G. Feitelson.
  “Backfilling Using System-Generated Predictions Rather than User Runtime Estimates”
  In IEEE Transactions on Parallel and Distributed Systems (TPDS), 18(6), pp. 789-803, Jun 2007.
• Yoav Etsion and Dror G. Feitelson.
  “Probabilistic Prediction of Temporal Locality”.
  In IEEE Computer Architecture Letters (CAL), 6(1), pp. 17-20, May 2007.
• Yoav Etsion, Dan Tsafrir, Scott Kirkpatrick, and Dror G. Feitelson.
  “Fine Grained Kernel Logging with KLogger: Experience and Insights”
  In 2nd EuroSys, pp. 259-272, Mar 2007. Accompanied by the KLogger tool.

2006

• Yoav Etsion, Dan Tsafrir, and Dror G. Feitelson.
  “Process Prioritization Using Output Production: Scheduling for Multimedia”.
  In ACM Trans. on Multimedia Computing, Communications, and Applications. (TOMCCAP), 2(4), pp. 318-342, Nov 2006.
• Eitan Frachtenberg and Yoav Etsion.
  Hardware Parallelism: Are Operating Systems Ready? (Case Studies in Mis-Scheduling) .
  In 2nd Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), pp. 7-15, Jun 2006.

2005

•  Dan Tsafrir, Yoav Etsion, and Dror G. Feitelson.
  “Modeling User Runtime Estimates”.
  In 11th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Jun 2005.
  D. G. Feitelson, E. Frachtenberg, L. Rudolph, and U. Schwiegelshohn (Eds.), pp. 1-35, Springer-Verlag, 2005. Lecture Notes in Computer Science Vol. 3834.
• Dan Tsafrir, Yoav Etsion, Dror G. Feitelson, and Scott Kirkpatrick.
  “System Noise, OS Clock Ticks, and Fine-Grained Parallel Applications”
  In the 19th Intl. Conf. on Supercomputing (ICS), pp. 303-312, Jun 2005.
• Dan Tsafrir, Yoav Etsion, and Dror G. Feitelson.
  “General Purpose Timing: The Failure of Periodic Timers”.
  Technical Report 2005-6, School of Computer Science and Engineering, The Hebrew University of Jerusalem, Feb. 2005.

2004

• Yoav Etsion, Dan Tsafrir, and Dror G. Feitelson.
  “Desktop Scheduling: How Can We Know What the User Wants?”.
  In the 14th ACM International Workshop on Network and Operating Systems Support for Digital Audio and Video (NOSSDAV), pp. 110-115, Jun 2004.

2003

• Yoav Etsion, Dan Tsafrir, and Dror G. Feitelson.
  “Effects of Clock Resolution on the Scheduling of Interactive and Soft Real-Time Processes”.
  In the Intl. Conf. on Measurement & Modeling of Computer Systems (SIGMETRICS), pp. 172-183, Jun 2003.

2001

• Yoav Etsion and Dror G. Feitelson.
  “User-Level Communication in a System with Gang Scheduling”.
  In the 15th Intl. Parallel and Distributed Processing Symp. (IPDPS), Apr 2001.

1999

• D. G. Feitelson, A. Batat, G. Benhanokh, D. Er-El, Y. Etsion, A. Kavas, T. Klainer, U. Lublin, and M. A. Volovic.
  The ParPar system: A software MPP.
  In High Performance Cluster Computing, Vol 1: Architectures and Systems, Rajkumar Buyya (Ed.), pp. 754-770, Prentice-Hall, 1999.Translated to Chinese.
•  Yoav Etsion, Michael Raizman, and Dror G. Feitelson.
  Topology and Routing in Clusters: From Theory to Practice.
  Technical Report 99-??, School of Computer Science and Engineering, The Hebrew University of Jerusalem, Dec 1999.